1. Field of the Invention
The present invention relates to an analog/digital converter for converting an analog input signal to a digital signal and, more specifically, to a serial-to-parallel type analog/digital converter converting an analog input signal by dividing the signal into upper bits and lower bits.
2. Description of the Background Art
As digital image processing technique has been developed recently, A/D converters capable of high speed operation and having high resolution have come to be in great demand. A/D converters capable of high speed operation includes flash type and serial-to-parallel type.
In a flash A/D converter, the number of comparators increases exponentially as the number of bits increases, in order to provide high resolution. Therefore, it is difficult to provide a compact semiconductor integrated circuit. In a serial-to-parallel type A/D converter, the number of comparators can be significantly reduced as compared with the flash converter, since analog input signals are divided into upper bits and lower bits to be subjected to A/D conversion. Therefore, a compact semiconductor integrated circuit can be realized by using the serial-to-parallel type converters.
FIG. 5 is a block diagram showing a conventional serial-to-parallel A/D converter. This example has a 4-bit structure. Referring to the figure, the analog/digital converter (hereinafter referred to as an A/D converter) includes a semiconductor substrate A, voltage comparators M1, M2 and M3 for upper bits, voltage comparators N1, N2 and N3 for lower bits, a voltage terminal T1 for supplying a predetermined reference voltage Vref-, a voltage terminal T2 for supplying a reference voltage Vref+, resistors R0-R15 connected in series between voltage terminals T1 and T2, switches SW10 to 12, SW20 to 22, SW 30 to 32 and SW40 to 42 for selecting reference voltages to voltage comparators N1-N3 for the lower bits, an encoder 1 for the upper bits, and an encoder 2 for the lower bits. Each of the voltage comparators M1-M3 and each of the voltage comparators N1-N3 has two input terminals, one of which is connected to receive a reference voltage divided by the resistors and, the other input terminal is commonly connected to an analog signal input terminal Tin. Resistors R0-R3 constitute a group, R4-R7 constitute another group, R8-R11 form still another group, and resistors R12-R15 constitute still another group. The groups of resistors R0-R3, R4-R7, R8-R11 and R12-R15 divide a voltage applied between voltage terminals T1 and T2, and generates reference voltages Vm1, Vm2 and Vm3 for the upper bits. The reference voltages Vm1 to Vm3 for the upper bits generated in this manner are supplied to voltage comparators M1-M3, respectively, and compared with an analog signal Vin by respective voltage comparators M1-M3. When Vin&gt;reference voltage, "1" ("H" level signal) is output, and when Vin.ltoreq.reference voltage, "0" ("L" level signal) is output. Encoder 1 for the upper bits encodes results P1-P3 of comparison by voltage comparators M1-M3 and provides upper 2 bits of digital outputs D2 and D3. Encoder 1 also generates signals S0-S3 for selecting reference voltages for the lower bits based on the results P1-P3 of the voltage comparison, and provides the signals S0-S3 to switches SW10-SW12, SW20-SW22, SW30-SW32, and SW40-SW42, respectively. The switches turn on when the corresponding one of the signals S0-S3 is "1", and turns off when the signal is "0". The reference voltages Vn1, Vn2 and Vn3 for the lower bits selected by the selecting signals S0-S3 are supplied to voltage comparators N1-N3, respectively. Each of the comparators N1-N3 compares the selected reference voltage with the analog input signal Vin. When Vin&gt;reference voltage, it outputs "1", and when Vin.ltoreq.reference voltage, it outputs "0". The results Q1-Q3 of such comparisons are supplied to encoder 2 for the lower bits, and lower 2 bits of digital outputs D0 and D1 are provided from encoder 2. FIG. 6 is a truth table of encoder 1 for the upper bits, and FIG. 7 is a truth table of encoder 2 for the lower bits.
Assume that the analog input signal Vin is at a potential between a node X1 of resistors R9 and R10, and a node X2 of resistors R10 and R11. Digital outputs at this time will be described. Since analog input signal Vin satisfies the condition Vm2&lt;Vin&lt;Vm3, the results of comparisons from voltage comparators M1-M3 will be P1="1", P2="1" and P3="0". From the truth table of FIG. 6, digital outputs of the upper bits will be D2="0" and D3="1". As to the signals S0-S3 for selecting the reference voltages, the switch S2 only attains "1", and other signals attain "0". Therefore, switches SW30-SW32 are turned on, and respective nodes of resistors R8-R11 are connected to voltage comparators N1 to N3. Consequently, reference voltages Vn1 to Vn3 are respectively supplied to voltage comparators N1 to N3. At this time, the analog input signal Vin satisfies the relation Vn2&lt;Vin&lt;Vn3, and therefore results of comparison from voltage comparators N1 to N3 will be Q1="1", Q2="1" and Q3="0". Consequently, digital outputs of the lower bits will be D0="0" and D1="1", in accordance with FIG. 7. Thus "1010" are provided as digital signals D3-D0.
However, in the A/D converter shown in FIG. 5, A/D conversion error arises from the layout of various elements on the semiconductor substrate. More specifically, interconnection of the power supply, and the positions and directions of comparators M1-M3 and N1-N2 cause a difference in precision of comparison, a difference in offset voltages between comparators M1-M3 for the upper bits and comparators N1-N3 for lower bits, and therefore, a significant error is likely to occur in a conversion code at the interface between the upper and lower bits. In order to solve this problem, a method has been proposed in which the range of measurement of the lower bits is enlarged to 3LSB to provide a correction code with respect to 1LSB of the upper bits, and the upper bits are corrected by this correction code. However, enlargement to 3LSB makes circuit structure complicated, and hence layout becomes difficult.
In addition, in this method, the time for conversion for the upper bits differs from that for the lower bits. Therefore, a highly precise sample/hold circuit for retaining the analog signal must be provided in the preceding stage of the A/D converter.
In order to solve the problem of sampling and holding, a method is known in which sample/hold circuits are distributed to respective comparators. This method is especially advantageous when a chopper type comparator is employed in a CMOS circuit, since a chopper type comparator contains, because of its principle of operation, a sample/hold circuit.
FIG. 8 shows an example of the above mentioned chopper type comparator. The comparator includes an inverter 3 having a P channel MOSFET and an N channel MOSFET; a switching circuit S1 connected to a reference voltage Vref; a switching circuit S2 connected to an analog signal input terminal Tin; a switching circuit S3 connected between an output and an input of inverter 3; and a coupling capacitance Cs connected between outputs of switching circuits S1 and S2 and the input of inverter 3. The switching circuits S1, S2 and S3 switch in response to switching pulses CP1 and CP2 shown in FIG. 9, respectively. Switching pulses CP1 and CP2 have a complementary phase relation, and when switching circuit S1 is on, switching circuits S2 and S3 are turned off. Therefore, switching circuit S1 and switching circuits S2 and S3 are controlled complementarily. Such a voltage comparator operating in this manner is called a chopper type comparator.
The operation of the chopper type comparator will be described. When switching circuits S2 and S3 are turned on by the switching pulse CP2, the voltage at input and output terminals of inverter 3 are set to the level of the logic threshold value Vth of inverter 3. Consequently, a difference between the analog input signal Vin and the logic threshold level Vth of inverter is charged in the capacitor Cs. At this time, the charge voltage Vi of the capacitor Cs will be EQU Vi=Vin-Vth
When switching circuit S1 is turned on by the switching pulse CP1, a reference voltage Vref is applied to capacitor Cs. Consequently, the charge voltage V2 of capacitor Cs will be EQU V.sub.2 =Vref-(Vin-Vth)=.DELTA.V+Vth
where, .DELTA.V=Vref-Vin
Inverter 3 inverts and amplifies a difference .DELTA.V between input signal Vin sampled and held by the capacitor Cs and switching circuit and reference voltage Vref. The amplified signal is provided to output terminal CO as a result of comparison.
Even in such a chopper type comparator, the above described problem of different offset voltages of comparator for the upper bits and the comparator for the lower bits cannot be solved.
When there is generated a time difference between a control signal for the upper bits of the sample/hold circuit and a control signal for the lower bits, the level of the analog input signal changes from the sampling/holding of upper bits to sampling/holding of the lower bits. Consequently, the level of the analog input signal goes out of the range of the selected reference voltage, causing an error in conversion.
Pipeline processing is known as a method of eliminating differences in conversion timing of the upper and lower bits (see A 20 Hz 8 bit Half-Flash CMOS A/D Converter, p55 ICD 88-8). An A/D converter having pipeline processing function disclosed in this article includes two comparators for upper bits and two comparators for lower bits. The two comparators operate alternately. Therefore, the error derived from the difference in conversion timing described above can be prevented, and in addition, time for A/D conversion can be reduced.
However, since there are two comparators for the upper bits and two comparators for the lower bits, the sample/hold control signals for controlling respective comparators are complicated, and timing control is difficult. Consequently, errors likely to occur because of timing deviation of sampling/holding between upper bits and lower bits.